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power management 1 united states patent no. 6,441,597 www.semtech.com SC420A high speed, combi-sense tm , synchronous power mosfet driver for mobile applications power management features applications revision: april 1, 2004 the SC420A is a cost effective dual mosfet driver, in- corporating semtech?s patented combi-sense tm technol- ogy, designed for switching high and low side power mosfets in step-down switching regulators. a 30ns max propagation delay from input transition to the gate of the power fet?s guarantees operation at high switching frequencies. internal overlap protection circuit prevents shoot-through from vin to gnd in the main and synchro- nous mosfets. high current drive capability allows fast switching, thus reducing switching losses at high frequencies without causing thermal stress on the driver. the high voltage cmos process allows operation up to 27 volts, making the SC420A suitable for adaptor pow- ered applications. under-voltage-lockout and over-tem- perature shutdown features are included for proper and safe operation. the SC420A is offered in a space saving mlp-12 package. u high efficiency u shutdown mode for increased power saving u fast rise and fall times (10ns typical with 3000pf load) u 5v gate drive u ultra-low (<30ns) propagation delay (bg going low) u adaptive and programmable non-overlapping gate drives provide shoot-through protection u floating top drive switches up to 27v u high frequency operation allows use of small inductors and low cost ceramic capacitors u under-voltage lockout u low quiescent current u mlp packaging provides superior thermal perfor- mance in a small footprint u high efficiency portable and notebook computers u battery powered applications description conceptual application circuit figure 1 vout gnd pwm fb vin cdelay en co vin2 vin bst tg drn bg vpn en vin2 cdelay rvpn cvpn cbst cl m1 m2 l1 sc42 0a d1 vin cs - cs+ combi - sense tm controller ic
2 ? 2004 semtech corp. united states patent no. 6,441,597 www.semtech.com power management SC420A electrical characteristics absolute maximum ratings unless specified: -40 o c < t j < 125c; v in = 5v; 0v < v drn < 25v parameter symbol conditions min typ max units power supply supply voltage vin 4.75 5 6 v vin2 27 v quiescent current, operating (static) iq op co = 0v, en > 2.2v 2.3 ma quiescent current, shutdown iq sd co = 0v, en = 0v 0.2 20 m a exceeding the specifications below may result in permanent damage to the device, or device malfunction. operation outside of the parameters specified in the electrical characteristics section is not implied. parameter symbol conditions min max units vin2 supply voltage vin2 30 v bst to pgnd 40 v bst to drn vin + 2 v drn to pgnd t pulse <100ns - 5 34 v static - 2 30 tg drn - 0.3 bst + 0.3 v bg - 0.3 vin + 0.3 v vpn to pgnd vpn 30 v vin to pgnd vin 7 v en, co, cdelay - 0.3 vin + 0.3 v continuous power dissipation p d tamb = 25 o c,t j = 125 o c 0.66 w tcase = 25 o c, t j = 125 o c 2.56 thermal resistance junction to case q jc 3 o c/w thermal resistance junction to ambient (1) q ja 48 o c/w operating junction temperature range t j - 40 125 o c storange temperature range t stg - 65 150 o c peak ir reflow (10 - 40 sec) t irreflow 260 o c note: (1) performance when used according to manufacturing guidelines, refer to applications information section for more information
3 ? 2004 semtech corp. power management SC420A united states patent no. 6,441,597 www.semtech.com electrical characteristics (cont.) unless specified: -40 o c < t j < 125c; v in = 5v; 0v < v drn < 25v parameter symbol conditions min typ max units under voltage lockout start threshold (ramping up) vin 4.1 4.3 4.55 v hysteresis vhys 100 200 350 mv under-voltage lockout time delay vin ramping up (2) tpdh uvlo 2 m s vin ramping down (2) tpd luvlo 2 m s en high level input voltage v ih 2.0 v low level input voltage v il 0.8 v co high level input voltage 2.0 v low level input voltage 0.8 v thermal shutdown over temperature trip point (2) t otp 165 o c hysteresis (2) t hyst 10 o c high side driver (tg) peak output current (3) i pkh 1.5 1.7 1.9 a output resistance (3) r src_tg i = 100ma v bst -v drn = 5v 1.8 2.2 2.6 w r sink_tg v bst -v drn = 5v 0.6 0.8 1.0 rise time (3) tr tg cl = 3nf,v bst - v drn = 5v 12 16 20 ns fall time (3) tf tg 10 14 18 ns
4 ? 2004 semtech corp. united states patent no. 6,441,597 www.semtech.com power management SC420A electrical characteristics (cont.) parameter symbol conditions min typ max units propagation delay, tg going high (3) tpdhtg ctg = 3nf,bg = 0v 30 36 42 ns propagation delay, tg going low (3) tpdltg ctg = 3nf,drn = 0v 20 28 36 ns low-side driver (bg) peak output current (3) i pkl 1.8 2.0 2.2 a output resistance (3) r src_bg i = 100ma 1.8 2.2 2.6 w r sink_bg 0.55 0.7 0.95 rise time (3) tr bg c bg = 3nf 5 10 15 ns fall time (3) tf bg c bg = 3nf 2 5 8 ns propagation delay,bg going high (3) tpdh bg c bg =3nf, drn = 0v 21 28 35 ns propagation delay,bg going low (3) tpdl bg c bg = 3nf 20 25 30 ns shoot-thru protection (cdelay) shoot-thru protection delay time (2) tspd c cdelay open 15 20 30 ns programmed delay 1 ns/pf cdelay charge current i cdelay 350 500 650 m a virtual phase node (vpn) output resistance r src_vpn 65 w r sink_vpn 90 leakage i leak_vpn v in2 =27v 600 na unless specified: -40 o c < t j < 125c; v in = 5v; 0v < v drn < 25v notes: (2) guaranteed by design (3) temperature = 25 o c
5 ? 2004 semtech corp. power management SC420A united states patent no. 6,441,597 www.semtech.com pin configuration ordering information note: (1) only available in tape and reel packaging. a reel contains 3000 devices. device (1) package temp range (t j ) SC420Aimltrt (3) mlp-12 -40 to 125c top view (mlp-12) pin # pin name pin function 1 tg output gate drive for the switching (high-side) mosfet. 2 bst bootstrap pin. a capacitor is connected between bst and drn pins to develop the floating bootstrap voltage for the high-side mosfet. the capacitor value is typically between 0.1f and 1f (ceramic). 3 co logic level pwm input signal to the sc420 supplied by external controller. 4 vin2 input power (vbat) to the dc/dc converter. used as supply reference for internal combi-sense tm circuitry. connect as close as possible to drain of top switching mosfet. 5 en active high logic level input signal. a logic high enables tg and bg switching. a low level disables outputs and reduces quiescent current to iq sd 6 vpn virtual phase node. connect an rc between this pin and the output sense point to enable combi- sense tm operation. 7 cdelay the capacitance connected between this pin and gnd sets the additional propagation delay for bg going low to tg going high. total propagation delay =20ns + 1ns/pf. if no capacitor is connected, the propragation delay = 20ns. 8 vin input supply for the bottom drive and the logic. a 1m f-10 m f ceramic capacitor must be connected from this pin to pgnd, placed less than 0.5" from sc420. 9 bg output drive for the synchronous (bottom) mosfet. 10 pgnd ground. keep this pin close to the synchronous mosfets source. 11 n.c. no connect 12 drn this pin connects to the junction of the switching and synchronous mosfets . this pin can be subjected to a -2v minimum relative to pgnd without affecting operation. pin descriptions ( 2) this device is esd sensitive. use of standard esd handling precautions is required. (3) lead free package compliant with j-std-020b. qualified to support maximum ir reflow temperature of 260 o c for 30 seconds. cdelay bst bg vin vpn en vin2 drn n.c. pgnd tg co 1 2 3 9 8 7 4 5 6 12 11 10
6 ? 2004 semtech corp. united states patent no. 6,441,597 www.semtech.com power management SC420A block diagram timing diagram co bg tg tf tpdl tpdh tr tpdl tf tspd tr tg tg tg bg bg bg bg tpdh tg vpn tri - state tri - state vin cdelay co en bst tg drn bg pgnd steering/ logic overlap protection bandgap vref vref vpn vin2 vin vin vin vin vin
7 ? 2004 semtech corp. power management SC420A united states patent no. 6,441,597 www.semtech.com applications information fig 1: typical applications schematic fig 2: typical SC420A components
8 ? 2004 semtech corp. united states patent no. 6,441,597 www.semtech.com power management SC420A applications information combi-sense (lossless current sense) combi-sense is a method to sense the output current on a combination of power devices. there is no sense resistor and the current is sensed on: top mosfet, bot- tom mosfet and output inductor. an internal phase node vpn sends a signal which is inte- grated by the combi-sense network. this network con- sists of a resistor and capacitor in series, connected between vpn and the drn pins. the resulting signal is large, clean and not duty cycle sensitive. it can be used directly for close loop current mode control and current limit. fast switching drives as the switching frequency of pwm controllers is increased to reduce power supply volume and cost, fast rise and fall times are necessary to minimize switching losses (top mosfet) and reduce dead-time (bottom mosfet) losses. while low rds_on mosfet?s present a power saving, the mosfets die area is larger and the effective input capacitance of the mosfet is increased. often a 50% decrease in rds_on doubles the effective input gate charge, which must be supplied by the driver. the rds_on power savings can be offset by the switching and dead-time losses with a suboptimum driver. while discrete solution can achieve reasonable drive capabil- ity, implementing shoot-through, programmable delay and other housekeeping functions necessary for safe opera- tion can become cumbersome and costly. the SC420A presents a total solution for the high-speed, high power density applications. wide input supply range of 4.5v- 25v allows use in battery powered applications, new high voltage, distributed power supplies. shoot through protection the control input (co) to the SC420A is typically supplied by a pwm controller that regulates the power supply out- put. the timing diagram demonstrates the sequence of events by which the top and bottom drive signals are applied. the shoot-through protection is implemented by holding the bottom fet off until the voltage at the phase node (intersection of top fet source, the output inductor and the bottom fet drain) has dropped below 1v. this assures that the top fet has turned off and that a direct current path does not exist between the input supply and ground, a shoot-through condition dur- ing which both the top and bottom fet?s could be on momentarily. the top fet is also prevented from turn- ing on until the bottom fet is off. the top fet turn-on delay is internally set to 30ns (typical) and may be programmably extended by an external capacitor on the cdelay pin, the delay is increased by 1ns/pf. the en (enable) pin may be used to turn both tg and bg drives off. this lowers power consumption by reducing the quiescent current draw of the SC420A to iqsd. co undriven if the co pin is undriven it will be pulled to gnd by an internal pull down resistor. this will switch the bg pin high and the tg pin low. o ver temperature shutdown the SC420A will shutdown by pulling both driver?s low if its junction temperature, t j , exceeds 165c. the driv- ers will resume operation when t j declines below 155 o c. supply voltage the SC420A can operate from 4.75v to 6v. the v in pin bypass capacitor must also be less than 0.5in away from the SC420A. the ground node of this capacitor, the SC420A pgnd pin and the source of the bottom fet must be very close to each other, preferably with com- mon pcb copper land with multiple vias to the ground plane (if used). the parallel schottky (if used) must be physically next to the bottom fet?s drain and source pins. any trace or lead inductance in these connections will drive current away from the schottky and allow it to flow through the fet?s body diode, thus reducing efficiency. preventing inadvertent bottom gate turn-on at high vin2 input voltages, (12v and greater) a fast turn- on of the top fet creates a positive going spike on the bottom fet?s gate through the miller capacitance, crss of the bottom fet. the voltage appearing on the gate due to this spike is: ) ( * ciss crss crss vin v spike + =
9 ? 2004 semtech corp. power management SC420A united states patent no. 6,441,597 www.semtech.com applications information (cont.) where ciss is the input gate capacitance of the bottom fet. this is assuming that the impedance of the drive path is too high compared to the instantaneous imped- ance of the capacitors, since dv/dt and thus the effective frequency is very high. if the bg pin of the SC420A is very close to the bottom fet, vspike will be reduced depending on trace inductance, rate of rise of current, etc. a capacitor may be added from the gate of the bottom fet to its source, preferably less than 0.5in away. this capacitor will be added to ciss in the above equation to reduce the effective spike voltage. the bottom mosfet must be selected with attention paid to the crss/ciss ratio. a low ratio reduces the miller feedback and thus reduces vspike. also mosfets with higher turn-on threshold voltages will conduct at a higher voltage and will not turn on during the spike. a zero ohm bottom fet gate resistor will obviously help keeping the gate voltage low during off time. ultimately, slowing down the top fet by adding boost re- sistance will reduce di/dt which will in turn make the effec- tive impedance of the capacitors higher, thus allowing the bg driver to hold the bottom gate voltage low. it does this at the expense of increased switching times (and switch- ing losses) for the top fet. the top mosfet source must be close to the bottom mosfet drain to prevent ringing and the possibility of the phase node going negative. this frequency is deter- mined by: far negative, thus causing improper operation, double puls- ing or at worst driver damage. on the SC420A, the drain node, drn, can go as far as 2v below ground without affecting operation or sustaining damage. the ringing is also an emi nuisance due to its high reso- nant frequency. adding a capacitor, typically 1000- 2000pf, in parallel with coss of the bottom fet will of- ten eliminate the emi issue. prevent driver overvoltage the negative voltage spikes on the phase node adds to the bootstrap capacitor voltage, thus increasing the volt- age between vbst - vdrn. this is of special importance if higher boost voltages are used. if the phase node negative spikes are too large, the voltage on the boost capacitor could exceed device?s absolute maximum rat- ing of 7v. to eliminate the effect of the ringing on the boost capacitor voltage, place a 1 - 10 ohm resistor be- tween boost schottky diode and v in to filter the negative spikes on drn pin. initially populate it by 0 ohm. alter- nately, a silicon diode, such as the commonly available 1n4148 can substitute for the schottky diode and elimi- nate the need for the series resistor. proper layout will guarantee minimum ringing and elimi- nate the need for external components. use of surface mount mosfets, while increasing thermal resistance, will reduce lead inductance as well as radiated emi. oss st st ring c l coss l sqrt f * 2 1 ) * ( * 2 ( 1 p = p = -where: l st = the effective stray inductance of the top fet added to trace inductance of the connection between top fet?s source and the bottom fet?s ground connection. c oss = drain to source capacitance of the bottom fet. if there is a schottky used, the capacitance of the schottky is added to this value although this ringing does not pose any power losses due to a fairly high q, it could cause the phase node to go too
10 ? 2004 semtech corp. united states patent no. 6,441,597 www.semtech.com power management SC420A applications information (cont.) vccvid regulator sys_pwrgd vr_on v 3 sc1403 vid_pwrgd co v 5 combi - sense tm controller en sc420 a en v cc - core vccpwrgd detailed information on manufacturing and rework of pcbs using the mlp package can be found in the mlp application note ?comprehensive user?s guide - micro lead frame package?. please contact your local semtech representative to obtain a copy of this application note. start-up sequencing proper sequencing of the combi-sense tm controller and SC420A driver during both start-up and shut-down is very important. in general, the design must ensure that the driver powers up (during start-up) before the controller does, and that the driver powers down last during shut-down. this ensures that the driver will never issue gate drive pulses that are not well-controlled. in general it is recommended that the vcc?s for the combi- sense controller and SC420A be connected to the same (5v) supply. if the en controls are not used (tied high) then the uvlo settings for the controller and driver will guarantee the proper sequencing (the SC420A maximum uvlo value is guarantee d to be lower than the combi- sense tm controller minimum uvlo value). for absolute guarantee of proper sequencing it is recom- mended that the en controls be used as shown in the following block diagram. with this arrangement the de- layed pwrgd signal from the vccvid regulator is used to enable both ics. the soft-start time established for the controller ensures it will come up well after the SC420A. during power-down de-assertion of vid_pwrgd will en- sure simultaneous disabling of the combi-sense tm control- ler and SC420A. manufacturing guidlines
11 ? 2004 semtech corp. power management SC420A united states patent no. 6,441,597 www.semtech.com applications information (cont.) component selection for SC420A application: high side mosfet (lsfet) the SC420A is usually used for low duty cycle ( ~ 10% ) applications. so the rds (on) of the high side mosfet is not a parameter of significant importance. a 10 ? 25 m rds for the hsfet is acceptable depending on the load current. minimum qg for the hsfet is important for component selection. typical range is 10 ? 25 nc. low side mosfet (lsfet) rds is the critical selection parameter for lsfet. it should be as low as possible for reduction of conduction losses and hence increase efficiency. typical range is 1 ? 3 m. rg is another important parameter for lsfet. it should be as low as possible as this will give better efficiency. typical range 0.1 ? 2 w . ratio of qgd/qgs is third parameter of consideration. as the duty cycle for the application increases, require- ments for the two fets become more similar; however, switching charge will always be more important to the hsfet since it switches into the full voltage, and the lsfet always switching into the near zero voltage. boost capacitor (cbst) boost capacitor is important for SC420A application as shown in the above figure. it is a good design rule to have boost capacitance at least 100 x the cgs for the hsfet. boost resistor (rbst) boost resistance is important and depends on the layout. we recommend always designing with the resistor as shown in the above circuit to help minimize emi when the hsfet turns on. the value required is layout dependant. bottom gate resistor (rbg) bg resistance is normally not required, but may be needed for damping for long bg trace runs. we recommend one rbg for each lsfet only when the maximum length of the bg trace is > 1 inch. populate with 0 w initially. top gate resistor (rtg) tg resistance is not generally required, as rbst can take care of the rising edge. we recommend one rtg for each hsfet only when the maximum length of the tg trace > 2 inches. populate with 0 w initially. boost diode (dbst) boost diode as shown in the above figure is required and should have a very low forward voltage drop. this increases the amount of charge on cbst capacitor. delay capacitor (cdly) delay capacitor is not added in a typical application. this option is useful to control the delay between the bg falling and tg rising edges. cdly is used for very high capacitance lsfets to ensure bg is below vth of the fet before tg turns on. decoupling capacitors (c1,c3) these are de-coupling capacitors present in the circuit. place as close to SC420A as possible. typical rating is 1uf/ 10v for c1 and 0.1uf /25v for c3.
12 ? 2004 semtech corp. united states patent no. 6,441,597 www.semtech.com power management SC420A applications information (cont.) critical component recommendations for SC420A application component manufacturer series or part number high side mosfet, hsfet international rectifier fairchild semiconductor siliconix infenion technologies depends on application low side mosfet, lsfet international rectifier fairchild semiconductor siliconix infenion technologies depends on application boost capacitor, cbst various x5r or better boost diode, dbst various schottky, 200ma or greater delay capacitor, cdly various npo ceramic decoupling capacitors, c1,c3 various x5r or better critical supplier contacts company contact international rectifier web: http://www.irf.com/product-info/ phone: (310) 726-8000 panasonic web: http://www.panasonic.com/pic/ecg/ phone: (201) 348-7522 irc web: http://www.irctt.com phone: (888) 472-4376 kernet web: http://www.kernet.com/ phone: (864) 963-6300 sanyo web: http://www.sanyovideo.com/ phone: (619) 661-6835 tdk web: http://www.component.tdk.com/components/components.html phone: (847) 390-4373 vishay/dale web: http://www.vishay.com/brands/dale phone: (402) 564-3131 vishay/siliconix web: http://www.vishay.com/brands/siliconix phone: (800) 554-5565
13 ? 2004 semtech corp. power management SC420A united states patent no. 6,441,597 www.semtech.com applications information (cont.) fig 3: typical layout schematic for SC420A layout guidelines as shown in the above layout the traces used for interconnections are not identical to each. the layout using the above traces has significant advantages. the traces used to interconnect c1, dbst, cbst, rbst, vcc, gnd, and vbat are wider and heavy. this is done to reduce the resistance and inductance of the current path. as a result the voltage drop of the traces is significantly reduced. this arrangement charges the cbst capacitor faster. because of this, the fet gate capacitances are also charged and discharged faster, improving the efficiency of the system. ceramic x7r capacitors are a good choice for supply bypassing near the chip. wider traces are also used for tg and bg connects. this is essential to decrease the delay of signal through the trace and allow rapid charge and discharge of the fet capacitance. inductance is usually the dominant impedance in the time range of interest (~10ns). as a result, run the tg and bg connections with a minimum aspect ratio (length to width) of 20:1. this results in a 50 mil trace for a one inch connection. in addition, minimize the loop area of the gate drive loop. this is easy with bg, since the return path for the current is gnd. in the case of tg, the return path for drivercurrent is drn, so run these traces together, as closely as possible. vias represent significant inductance and are to be avoided wherever possible. bg is especially important because when the hsfet switches off, the high dv/ dt of the drn node will force current into the lsfet gate via cgd. a large inductance in the bg trace will prevent the driver from holding bg down at this time. the signal level traces are not critical because the current levels are much smaller. we can also see vias (circular dots) present in the layout. the vias are important for interconnection between different layers of the pcb. also they are important in heat transfer and aid in running the system cooler.
14 ? 2004 semtech corp. united states patent no. 6,441,597 www.semtech.com power management SC420A applications information (cont.) timing waveforms measured in a system the following waveforms were noted using a 3-phase sc2647 combi-sense? pwm controller system. typical operating conditions for this system are input voltage, vin = 10 ? 25v output current, iout = 0 ? 52a output voltage, vout = 0.8 ? 1.85v timing diagram, vin = 10v, iout = 0, vout = 1.45v timing diagram, vin = 10v, iout = 10a, vout = 1.45v timing diagram, vin = 10v, iout = 20a, vout = 1.45v timing diagram, vin = 10v, iout = 30a, vout = 1.45v component manufacturer series or part number high side mosfet (each phase) international rectifier 2 irf7811av's, total gate capacitance = 3.602 nf low side mosfet (each phase) fairchild semiconductor 2 fds7066's, total gate capacitance = 9.946 nf output inductor (each phase) panasonic series 2334q, l= 700nh, rl~ 1mohm controller semtech sc2647 list of components used for above application
15 ? 2004 semtech corp. power management SC420A united states patent no. 6,441,597 www.semtech.com outline drawing - mlp-12
16 ? 2004 semtech corp. united states patent no. 6,441,597 www.semtech.com power management SC420A contact information pcb footprint - mlp-12 semtech corporation power management products division 200 flynn road, camarillo, ca 93012 phone: (805)498-2111 fax (805)498-3804 SC420A footprint note: this land pattern is for reference purposes only. consult your manufacturing group to ensure you meet your company?s manufacturability guidelines.

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